1. Field of the Invention
The invention relates to a method of fabricating micromechanical components with free-standing microstructures or membranes under predeterminable mechanical stresses.
2. The Prior Art
Aside from bulk micromachining in which three-dimensional structures are etched out of a wafer by anisotropic selective etching solutions, so-called surface micromachining has gained ever increasing significance. With this technology, free-standing moveable microstructures may be fabricated on a substrate surface. Sandwich systems of distinct layers which may be etched with respect of each other form the basis for these structures. After structuring of the uppermost layer (e.g. of polysilicon) the sacrificial layer positioned beneath it (e.g. silicon dioxide) is removed by a wet chemical process, so that free-standing structures are formed which may be shaped like bridges or tongues.
The material chiefly used for these mechanical structures is polycrystalline silicon (polysilicon). The layer thicknesses of the polysilicon layers required for this purpose range between several μm up to several 10 μm.
Polysilicon layers are also used in electronic components. In that case, the required layer thicknesses are in the range of several 100 nm at a maximum. The layers are precipitated in low pressure chemical vapor deposition (LPCVD) reactors. However, the LPCVD reactors have relatively low layer precipitation rates of about 20 nm/min. In these systems, the layer thickness attainable within acceptable process intervals is, therefore, limited to about 2 μm. Hence, for applications requiring layer thicknesses of up to several 10 μm, this precipitation process is not suitable.
A further disadvantage of polysilicon layers fabricated in these systems resides in the resulting mechanical stress in the polysilicon. The standard process temperatures utilized in microelectronics range between 630° C. and 650° C. At these temperatures, the precipitated polysilicon layer is always subject to compressive stress (see, e.g., H. Guckel et al., Tech. Digest, 4th Int. Conf. Solid-State Sensors and Actuators (Transducers 87), Tokyo, 2-5 Jun. 1987, pp. 277). However, in many areas of application of micromechanics it is tensile stresses which are desired in the material, since compressive stress leads to buckling of membranes or bridge structures, for instance.
A known process for fabricating polysilicon layers with tensile stresses as described by H. Guckel et al., 1988, Solid State Sensor & Actuator Workshop, Hilton Head Island, S.C., 6-9 Jun. 1988, pp. 96, involves precipitation of the silicon at temperatures below 580° C. At these temperatures, the precipitated layer is not polycrystalline but more or less amorphous. A subsequent temperature treatment at 900° C. leads to crystallization. The rearrangement of the silicon atoms taking place in this process is accompanied by a volume contraction which, in turn, leads to tensile stresses within the material.
On the other hand, if annealing is thereafter undertaken at temperatures in excess of 1,000° C., the tensile stresses will be converted again into compressive stresses.
A further process of controlling stress in a layer of LPCVD polysilicon is described by P. Kruvelitch et al., Tech. Digest, 6th Int. Conf. Solid State Sensors and Actuators (Transducers 91), San Francisco, 23-27 Jun. 1991, pp. 949. By appropriately selecting the precipitation temperature, tensile stress (T about 605° C.) or compressive stress (T>620° C.) is generated in the layer.
Different tests have shown, however, that the tension values generated in the polysilicon layer by the mentioned processes can only be poorly reproduced. Moreover, the layer thickness which may be obtained within reasonable processing times is limited to about 2 μm, so that such processes are not suitable for free-standing structures requiring layer thicknesses up to several 10 μm.
A process of making thick polysilicon layers (1-15 μm) is known from T. I. Kamins et al., Thin Solid Films, 16, 147 (1973), in which the polysilicon is precipitated by gaseous phase deposition (CVD) (as compared to LPCVD) at increased pressure. Deposition rates of 60-500 nm/min are obtained by this process, so that polysilicon layers having a thickness of 15 μm may be fabricated.
No indication is given, however, in which manner the stresses in the polysilicon layers may be affected during deposition.